139.59.127.108:8080

!C99Shell v. 2.5 [PHP 8 Update] [24.05.2025]!
Software: Apache/2.4.41 (Ubuntu). PHP/8.0.30 uname -a: Linux apirnd 5.4.0-204-generic #224-Ubuntu SMP Thu Dec 5 13:38:28 UTC 2024 x86_64 uid=33(www-data) gid=33(www-data) groups=33(www-data) Safe-mode: OFF (not secure) /usr/src/linux-headers-5.4.0-204/include/dt-bindings/clock/ drwxr-xr-x Free 13.3 GB of 57.97 GB (22.95%) Encoder Tools Proc. FTP brute Sec. SQL PHP-code Update Self remove Logout


/* SPDX-License-Identifier: GPL-2.0+
 *
 * Copyright (C) 2015 Renesas Electronics Corp.
 */
#ifndef __DT_BINDINGS_CLOCK_R8A7795_CPG_MSSR_H__
#define __DT_BINDINGS_CLOCK_R8A7795_CPG_MSSR_H__

#include <dt-bindings/clock/renesas-cpg-mssr.h>

/* r8a7795 CPG Core Clocks */
#define R8A7795_CLK_Z            0
#define R8A7795_CLK_Z2            1
#define R8A7795_CLK_ZR            2
#define R8A7795_CLK_ZG            3
#define R8A7795_CLK_ZTR            4
#define R8A7795_CLK_ZTRD2        5
#define R8A7795_CLK_ZT            6
#define R8A7795_CLK_ZX            7
#define R8A7795_CLK_S0D1        8
#define R8A7795_CLK_S0D4        9
#define R8A7795_CLK_S1D1        10
#define R8A7795_CLK_S1D2        11
#define R8A7795_CLK_S1D4        12
#define R8A7795_CLK_S2D1        13
#define R8A7795_CLK_S2D2        14
#define R8A7795_CLK_S2D4        15
#define R8A7795_CLK_S3D1        16
#define R8A7795_CLK_S3D2        17
#define R8A7795_CLK_S3D4        18
#define R8A7795_CLK_LB            19
#define R8A7795_CLK_CL            20
#define R8A7795_CLK_ZB3            21
#define R8A7795_CLK_ZB3D2        22
#define R8A7795_CLK_CR            23
#define R8A7795_CLK_CRD2        24
#define R8A7795_CLK_SD0H        25
#define R8A7795_CLK_SD0            26
#define R8A7795_CLK_SD1H        27
#define R8A7795_CLK_SD1            28
#define R8A7795_CLK_SD2H        29
#define R8A7795_CLK_SD2            30
#define R8A7795_CLK_SD3H        31
#define R8A7795_CLK_SD3            32
#define R8A7795_CLK_SSP2        33
#define R8A7795_CLK_SSP1        34
#define R8A7795_CLK_SSPRS        35
#define R8A7795_CLK_RPC            36
#define R8A7795_CLK_RPCD2        37
#define R8A7795_CLK_MSO            38
#define R8A7795_CLK_CANFD        39
#define R8A7795_CLK_HDMI        40
#define R8A7795_CLK_CSI0        41
/* CLK_CSIREF was removed */
#define R8A7795_CLK_CP            43
#define R8A7795_CLK_CPEX        44
#define R8A7795_CLK_R            45
#define R8A7795_CLK_OSC            46

/* r8a7795 ES2.0 CPG Core Clocks */
#define R8A7795_CLK_S0D2        47
#define R8A7795_CLK_S0D3        48
#define R8A7795_CLK_S0D6        49
#define R8A7795_CLK_S0D8        50
#define R8A7795_CLK_S0D12        51

#endif /* __DT_BINDINGS_CLOCK_R8A7795_CPG_MSSR_H__ */

:: Command execute ::
Enter:	Select: